The present invention relates to techniques for reducing leakage current, and more particularly, to techniques for reducing leakage current through transistors in an on-chip impedance termination circuit.
Integrated circuits have input/output (IO) pins that are used to transmit signals into and out of the circuit. An external termination resistor is usually coupled to each IO pin to provide impedance termination. An impedance termination resistor reduces reflection of input signals on a signal line coupled to an IO pin. Signal reflection causes signal distortion and degrades overall signal quality.
The use of external resistors for termination purposes can be cumbersome and costly, especially for integrated circuits that have numerous IO pins. For example, external resistors typically use a substantial amount of board space. As a result, on-chip impedance termination techniques have been developed, because they occupy less board space.
Prior art integrated circuits have provided on-chip impedance termination by coupling a field-effect transistor to an IO pin. The gate voltage of the transistor is controlled by a calibration circuit to regulate the impedance of the on-chip transistor. On-chip transistors have also been applied across differential IO pins to provide impedance termination.
However, transistors that control on-chip impedance termination circuits can leak unwanted current through their drain/source-to-body diodes even when the transistors are disabled. Therefore, it would be desirable to provide on-chip impedance termination circuits that have reduced leakage current.